PHY
- EthTrcv Part 1 — Basics & Classification in the AUTOSAR Ethernet Stack
The opening post of the EthTrcv series: what an Ethernet transceiver is, how EthTrcv sits in the AUTOSAR Layered Architecture Model between EthIf and PHY hardware, and which PHY chips show up in real projects.
- EthTrcv — Master/Slave Configuration for 100BASE-T1
Why 100BASE-T1 links need a fixed master/slave role, how it is configured in the PHY register and in ARXML, and why a role conflict is the classic 'no link' bug in the field.
- EthTrcv — Reading MDIO and PHY Registers Directly
Register-level MDIO diagnostics for EthTrcv: reading standard and vendor registers, interpreting link status and error flags, and a case study of a link that refuses to come up.
- EthTrcv from the Hardware Side — PHY Architecture for Software Developers
What actually happens inside the PHY chip when EthTrcv_Init is called: the PMA/PCS/MDI architecture, link training on 100BASE-T1, and PHY-level power states — explained conceptually, without the electronics deep dive.
- EthTrcv Hardware Deep Dive — The Physical Interfaces of the PHY Chip
A hardware deep dive for software developers: what happens at PCB level when EthTrcv is configured — MAC interfaces, MDIO bus, line side, and the path of a frame through the PHY.