This post is part of the EthTrcv series and builds on the AUTOSAR basics post. It is aimed at software developers who configure EthTrcv on a daily basis but have never wanted to know exactly what happens at PCB level.
Anyone who sets an ARXML parameter like EthTrcvBusIdx to ETHTRCV_BUS_TYPE_RGMII
is making a hardware decision — even if it may not feel that way.
This post makes visible what lies behind these parameters.
The PHY Chip as Mediator
An Ethernet PHY chip sits exactly in the middle between two worlds:
SoC / Microcontroller Cable
┌─────────────────┐ ┌────────┐
│ Ethernet MAC │◄── MII/RMII/RGMII ─►│ PHY │◄── MDI ──► Twisted Pair
│ │◄── MDIO ────────── ─►│ Chip │
└─────────────────┘ └────────┘On the left side: digital interfaces to the MAC in the SoC. On the right side: analog interface to the cable. In the middle: everything that makes up the conversion — encoding, scrambling, signal shaping.
EthTrcv_Init initializes this chip.
What exactly happens during that process, this post explains from left to right.
The MAC-Side Interfaces (MII Family)
The MAC-side interface between SoC and PHY is standardized. IEEE 802.3 defines several variants — all under the umbrella term MII family.
MII — Media Independent Interface
The original from IEEE 802.3u (1995). Rarely found in new designs today, but essential for understanding its successors.
Signals: TX_CLK, TXD[3:0], TX_EN, TX_ER
RX_CLK, RXD[3:0], RX_DV, RX_ER, CRS, COL
Clock: 25 MHz (100 Mbit/s) / 2.5 MHz (10 Mbit/s)
Data width: 4 bits parallel (nibble)
Lines: ~16 data lines + control/clock linesWhy it is rarely built anymore: 16+ lines on the PCB, high routing effort, and on modern SoCs the GPIO pins are too valuable.
RMII — Reduced MII
Reduced variant with only 9 lines instead of 16+. Typical for smaller microcontrollers where GPIO pins are scarce.
Signals: REF_CLK (50 MHz, from PHY or external), TXD[1:0], TX_EN
RXD[1:0], CRS_DV, RX_ER
Clock: 50 MHz fixed (one clock for both directions)
Data width: 2 bits parallel
Note: MAC and PHY share a common 50 MHz reference clockThe 50 MHz REF_CLK must either be supplied by the PHY or fed in externally. Forgetting the clock or wiring it incorrectly means no link — and wondering why. |
RGMII — Reduced Gigabit MII
The dominant standard today for automotive Ethernet at 1 Gbit/s and for many modern 100 Mbit/s designs.
Signals: TXC, TXD[3:0], TX_CTL
RXC, RXD[3:0], RX_CTL
Clock: 125 MHz (1 Gbit/s) / 25 MHz (100 Mbit/s) / 2.5 MHz (10 Mbit/s)
Data width: 4 bits, DDR (Double Data Rate — data on rising AND falling edge)
Lines: 12 signals instead of MII's 16+DDR at 125 MHz delivers effectively 8 bits per clock cycle → 1 Gbit/s. This sounds elegant but has a catch: RGMII Timing Delays.
The specification requires that data must be delayed by 1.5–2 ns relative to the clock. This delay can be implemented in the PHY, in the MAC, or via PCB trace lengths — and is a common cause of sporadic transmission errors when the PCB layout is wrong.
In AUTOSAR this is not directly visible, but the EthTrcvBusIdx parameter selects among other things
whether internal PHY delays are activated or whether the MAC driver handles them.
SGMII / SerDes
For scenarios where PHY and MAC are further apart — typically with switch chips that aggregate multiple PHYs.
Signals: TX+ / TX- (differential), RX+ / RX- (differential)
Clock: 1.25 GBaud serial (8b/10b encoded → 1 Gbit/s payload)
Lines: 4 (two differential pairs)
Advantage: Longer PCB runs possible, fewer linesIn EthSwt configurations SGMII is more common than in simple EthTrcv setups.
Decision Guide: Which Interface for What?
| Interface | Max. Speed | Lines | Typical Use | Automotive Relevance |
|---|---|---|---|---|
MII | 100 Mbit/s | 16+ | Legacy | Rarely new |
RMII | 100 Mbit/s | 9 | Small MCUs | Medium (ECUs) |
RGMII | 1 Gbit/s | 12 | Application SoCs, 1000BASE-T1 | High (ADAS, Gateway) |
SGMII | 1 Gbit/s | 4 | Switch aggregation | High in zonal architecture |
The MDIO Bus
MDIO (Management Data Input/Output) is the control bus to the PHY.
This is where EthTrcv_Init runs — not over MII/RGMII.
SoC
│
├── MDC (Management Data Clock) ────────────► PHY 1
└── MDIO (Management Data I/O, bidirectional) ─► PHY 1
► PHY 2 (same line)
► PHY 3 (same line)Electrical Specification
Voltage: typically 3.3 V LVCMOS (or 1.8 V on modern SoCs)
MDC frequency: max. 2.5 MHz per IEEE, many PHYs tolerate up to 25 MHz
Pull-up: MDIO requires a pull-up resistor (typically 1.5 kΩ – 4.7 kΩ)
Bus load: up to 32 PHY addresses per MDIO bus possibleThe pull-up is critical: if it is missing, MDIO stays permanently low and all register reads
return 0xFF or 0x00 — which looks exactly like a misconfigured PHY.
Clause 22 vs. Clause 45
IEEE 802.3 defines two frame formats for MDIO:
Clause 22 (classic):
ST | OP | PHYAD[4:0] | REGAD[4:0] | TA | DATA[15:0]
2 2 5 5 2 16 bits32 PHY addresses, 32 registers per PHY. Sufficient for simple PHYs.
Clause 45 (extended):
ST | OP | PRTAD[4:0] | DEVAD[5:0] | TA | ADDR/DATA[15:0]
2 2 5 5 2 16 bitsClause 45 introduces a DEVAD (Device Address) — enabling 32 address spaces of 65536 registers each.
Mandatory for 1000BASE-T1 PHYs and all PHYs with safety or MACsec features.
Some SoC MAC drivers only natively support Clause 22. Clause 45 on such systems requires a workaround via "Clause 22 Preamble Suppression" — a common pitfall with newer PHY chips. |
Timing and MDC Frequency
MDC ───┐ ┌──┐ ┌──┐ ┌──┐ ┌──
└──┘ └──┘ └──┘ └──┘
MDIO ════╪═════╪═════╪════
Setup↑ ↑HoldSetup time (MDIO stable before rising MDC edge): min. 10 ns
Hold time (MDIO stable after rising MDC edge): min. 10 ns
With too high an MDC frequency or long PCB traces these times are violated. Symptom: register reads return corrupted values, PHY does not respond to init.
Multiple PHYs on One MDIO Bus
Each PHY has a 5-bit PHY address (0–31), often configured via hardware pins.
In ARXML this corresponds to the parameter EthTrcvPhyAddress.
SoC MDIO bus
├── PHY @ address 1 (PHYAD pins: 00001)
├── PHY @ address 2 (PHYAD pins: 00010)
└── PHY @ address 3 (PHYAD pins: 00011)Address conflicts (two PHYs with the same address) are a classic hardware bug: both PHYs respond simultaneously, the bus is corrupted, all MDIO reads return garbage.
The Line-Side Interfaces
On the other side of the PHY chip: the connection to the cable.
MDI — Medium Dependent Interface
MDI is the physical connection of the PHY to the transmission medium. The name says it all: from here everything is medium-dependent — the PHY standard defines the electrical properties of the signal on the line.
100BASE-T1 — The Automotive Single-Pair Interface
Classic 100BASE-TX uses two twisted wire pairs (TX and RX separate). 100BASE-T1 manages with a single twisted pair.
100BASE-TX: ──[TX+/TX-]── ──[RX+/RX-]── (2 pairs, ≈ RJ45 connector)
100BASE-T1: ──[T1+/T1-]── (1 pair, differential, bidirectional)Bidirectional operation on one pair is possible because the signal uses echo cancellation in the PHY — the chip subtracts its own transmit signal to isolate the receive signal.
Cable specification:
Impedance: 100 Ω (±15 %)
Maximum length: 15 m (standard), up to 40 m at reduced data rate
Cable type: Unshielded Twisted Pair (UTP), automotive-approved
AWG: typically AWG 22–241000BASE-T1
Same philosophy as 100BASE-T1, but at 1 Gbit/s over a single-pair cable. Uses PAM3 with a higher symbol rate, shorter maximum cable length (approx. 15 m). Increasingly used in vehicles for backbone connections (zonal controller → domain controller).
Connectors in the Vehicle
The cable has to be connected somewhere. In the automotive world there are established connector standards for this:
| Connector | Use | Relevance for Ethernet |
|---|---|---|
FAKRA | High-frequency coaxial, classically for antennas and cameras | Not for twisted-pair Ethernet — a common mix-up |
HSD (High Speed Data) | 4-pin connector, for data transmission in the vehicle | Used for 100BASE-T1 and USB, widely deployed |
MATEnet | TE Connectivity standard specifically for automotive Ethernet | Optimized for 100BASE-T1 / 1000BASE-T1, low insertion loss |
H-MTD | Compact, for tight installation situations | Increasingly used for 1000BASE-T1 in compact ECUs |
The connector affects signal integrity. An HSD connector with incorrect impedance matching can cause link issues at 1000BASE-T1 just as reliably as a defective cable. |
EMC Aspects
Software developers rarely think about EMC — hardware developers always do. The interface sits in the vehicle close to other interference sources (ignition system, DC/DC converters).
Common-Mode Filter (CMF): Mounted directly at the MDI connection. Suppresses common-mode interference on the line. Wrong or missing CMF → PHY has increased noise → sporadic bit errors.
ESD Protection: Transient Voltage Suppressor (TVS) or similar components at the connector. Protects the PHY from electrostatic discharge when plugging/unplugging. Mandatory in production applications — often omitted on development boards.
PCB Layout: The differential trace routing (T1+ / T1-) must be routed with exactly equal length (differential pair matching). Length mismatch > 150 mil → measurable signal quality degradation.
Power Supply and Voltage Levels
A modern automotive PHY chip typically has multiple supply domains:
VDD_IO 3.3 V — I/O level for MII/MDIO signals to MAC/SoC
VDD_Core 1.8 V — Internal core logic
VDD_PLL 1.8 V — PLL for clock generation (often separate rail)
VDD_MDI 3.3 V — Analog side, line couplingPower Sequencing
The power-on sequence is specified in the PHY datasheet and must be followed. Typical sequence:
1. Power up VDD_Core
2. Power up VDD_IO (≥ 100 µs after Core)
3. Power up VDD_MDI
4. Deassert hardware reset (RST_N)
5. Wait for PHY boot time (typically 1–5 ms)
6. MDIO access possible → EthTrcv_Init can startViolating the sequence → PHY boots in an undefined state.
Symptom: EthTrcv_Init returns but the link never comes up.
WakeUp Pin and INH Pin
Two pins that software developers should know, even if they never directly control them:
WakeUp Pin (WU):
Input on the PHY for an external WakeUp pulse.
When the ECU is in sleep and supports Ethernet WakeUp,
a specific pulse on this pin can wake the ECU up.
On the AUTOSAR side this is evaluated in EthTrcv_CheckWakeup.
INH Pin (Inhibit): Output of the PHY that controls the ECU’s voltage regulator. When the PHY goes to sleep it pulls INH low → voltage regulator shuts down → ECU sleeps. When WakeUp is detected the PHY asserts INH → voltage regulator starts → system wakes up.
WakeUp pulse on line
→ PHY detects pulse
→ PHY asserts INH
→ voltage regulator starts
→ SoC boots
→ EcuM calls EthTrcv_CheckWakeup
→ AUTOSAR WakeUp validation runs throughFrom Bit to Signal — a Frame Through the PHY
Finally, the complete path of an Ethernet frame through the PHY chip, from MAC handoff to differential signal on the line.
Step 1: MAC Hands Over Frame via RGMII
SoC MAC hands over: TXD[3:0] = nibble, TX_CTL = 1 (valid), TXC = 125 MHz
PHY receives 4 bits per clock edge (DDR) → 8 bits per clock cycle
At 125 MHz: 8 bits × 125,000,000 = 1,000,000,000 bits/s = 1 Gbit/sStep 2: PCS — Physical Coding Sublayer
The PCS prepares the bits for transmission:
Scrambling — pseudo-randomly shuffles the bit sequence, prevents DC bias
Encoding — for 100BASE-T1: no 8b/10b, instead direct PAM3 mapping with trellis code
Step 3: PMA — Physical Medium Attachment
The PMA converts the encoded bits into physical symbols:
PAM3 for 100BASE-T1:
Three voltage levels: +1 (positive), 0 (zero), -1 (negative)
Symbol rate: 66.67 MBaud (66.67 million symbols/second)
Each symbol: carries ~1.58 bits of information (log₂(3))
Payload: 100 Mbit/s after overheadThree levels instead of two — that is why 100 Mbit/s over a single-pair cable at only 66 MBaud symbol rate is possible.
Step 4: Echo Cancellation
Since transmitting and receiving happen on the same wire pair, the PHY must subtract its own transmit signal from the receive signal. This happens digitally inside the PHY with an adaptive filter — and is why 100BASE-T1 PHYs are significantly more complex than classic PHYs.
Step 5: Signal on the Line
Differential signal: T1+ and T1- with 100 Ω impedance
Amplitude: typically ±1 V (differential)
Frequency range: DC to ~66 MHz (main energy)Latency Through the PHY
RGMII → PCS → PMA → cable: typically 150–500 ns (depends on PHY chip and implementation)
Cable (15 m @ ~0.6c): approx. 80 ns
Receive side (cable → MAC): another 150–500 nsTotal latency for one frame: approx. 500 ns – 1.5 µs. Relevant for gPTP (Issue #14) where sub-microsecond accuracy is required.
Summary
| Interface | Key takeaway for software developers |
|---|---|
MII/RMII/RGMII | Choice affects the |
MDIO | Missing pull-up → all reads return garbage; check Clause 45 for modern PHY chips |
MDI / 100BASE-T1 | Single-pair, bidirectional via echo cancellation; cable impedance and connector are signal quality factors |
EMC | Common-mode filter at the connector is mandatory — if missing, problems only show up in vehicle EMC testing |
Power sequencing | Wrong order → PHY does not respond to init, no obvious error code |
WakeUp/INH pin | These pins control the ECU’s voltage regulator — AUTOSAR EcuM must be configured correctly |
Next in the EthTrcv series: EthTrcv Part 1 — Basics & Classification